Tim Mattox's Publications

My Ph.D. Dissertation:

Exploiting Sparseness of Communication Patterns for the Design of Networks in Massively Parallel Supercomputers

Ph.D., Electrical and Computer Engineering, University of Kentucky, August 2006.

Abstract:

A limited set of Processing Element (PE) pairs in a parallel computer cover the internal communications of scalable parallel programs. We take advantage of this property using the concept of Sparse Flat Neighborhood Networks (Sparse FNNs). Sparse FNNs are network designs that provide single-switch latency and full wire bandwidth for each specified PE pair, despite using relatively few network interfaces per PE and switches that have far fewer ports than there are PEs. This dissertation discusses the design problem, runtime support, and working prototype (KASY0) for Sparse FNNs. KASY0 not only demonstrated the claimed properties, but also set world records for its price/performance and performance on a specific application.

Parallel supercomputers execute many portions of an application simultaneously. For scalable programs, the more PEs the system has, the greater the potential speedup. Portions executing on different PEs may be able to work independently for short periods, but the performance desired might not be achieved due to delays in communication between PEs. The set of PE pairs that will communicate often is both predictable and small relative to the number of possible PE pairings. This sparseness property can be exploited in the design and implementation of networks for massively parallel supercomputers.

The sparseness of communicating pairs is rooted in the fact that each of the human-designed communication patterns commonly used in parallel programs has the property that the number of communicating pairs grows relatively slowly as the number of PEs is increased. Additionally, the number of pairs in the union of all communication patterns used in a suite of parallel programs grows surprisingly slowly due to pair synergy: the same pair often appears in multiple communication patterns. Detailed analysis of communication patterns clearly shows that the number of PE pairs actually communicating is very sparse, although the structure of the sparseness can be complex.

My Master's Thesis:

Synchronous Aggregate Communication Architecture for MIMD Parallel Processing

M.S.E.E., School of Electrical and Computer Engineering, Purdue University, August 1997.

Abstract:

A multitude of different parallel architectures have been proposed, and each works well for applications with the appropriate types of parallelism. However, to achieve the best possible speedup for a wide range of parallel applications, a parallel computer's hardware must be able to make effective use of most types of parallelism.

This thesis suggests that the most fundamental flaws of MIMD architecture can be corrected by the addition of a simple synchronous aggregate communication system. After reviewing the relationship between some basic architectural characteristics and the types of parallelism that they can support, a small set of synchronous aggregate communication operations are defined. The implementation and performance of the PAPERS1 prototype hardware, a very simple synchronous aggregate communication system for a MIMD cluster of PCs, is discussed in detail.

My Publications (Check my CV for an up-to-date list):