Marc Heijligers's Research Page


Biography

Marc Heijligers received his Masters in Information Technology from the Eindhoven University of Technology in 1991, and obtained his PhD in 1996. In his PhD thesis he investigated the use of optimization techniques for architectural synthesis.

He joined Philips Research in 1996, working on architectural synthesis for high-throughput video processing, then on he worked on C++ code analysis for IC design in the Electronic Design & Tools department. Since 2001, he is leader of the Systems on Silicon Integration cluster, working on topics such as low power design, cache management for multi-processor systems, embedded FPGAs, channel decoding, smart image processing, and strategical documents in the area of the semiconductors industry.

Since September 2006, Marc is working at NXP Semiconductors, where he is group manager of the IC-lab digital VLSI group.

CV

My CV is available on request.

Photograph

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Contact

Marc Heijligers
NXP Semiconductors, IC-lab
High Tech Campus 46
5656 AE Eindhoven

tel: +31 (0)40 27 25493
e-mail: marc.heijligers@nxp.com
Marc@Linkedin

Scientific Publications

WARNING: This section contains links to document files that may be covered by copyright. You may browse them at your convenience (in the same spirit as you may read a journal or a proceeding article in a public library). Retrieving, copying, or distributing these files, however, may violate the copyright protection law. We recommend that the user abides international law in accessing this directory.

- A. Molnos, S. D. Cotofana, M.J.M. Heijligers, Compositional, dynamic cache management for embedded chip multiprocessors, Proceedings of Design, Automation and Test in Europe 2008 (DATE 08), pp. 991-996, March 2008

- A. Abbo, R. Kleihorst, V. Choudhary, L. Sevat, P. Wielage, S. Mouy, B. Vermeulen, and Marc Heijligers, Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis, IEEE Journal of Solid-State Circuits, Vol. 43, No. 1, January 2008

- I. Diaz, A. Danilin, R. Kleihorst, and M. Heijligers, “An embedded lowpower highly efficient object tracker for surveillance systems,” in International Conference on Distributed Smart Cameras,
(Vienna, Austria), Sept. 2007

- A. Molnos, S. D. Cotofana, M.J.M. Heijligers, J.T.J. Eijndhoven, Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors, Transactions on High-Performance Embedded Architectures and Compilers I, pp. 279-297, August 2007

- Abbo, A. Kleihorst, R. Choudhary, V. Sevat, L. Wielage, P. Mouy, S. Heijligers, M., XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis, Solid-State Circuits Conference, 2007. ISSCC 2007, 11-15 Feb. 2007

- Richard Kleihorst, Ben Schueler, Alexander Danilin, Marc Heijligers, Smart Camera More with High Performance Vision System, Workshop on Distributed Smart Cameras, October 2006.

- M.J.M. Heijligers, Design challenges for wireless smart cameras, 6th International Forum on Application-Specific Multi-Processor SoC, Estes Park, 14 - 18 August, 2006

- A. Molnos, S. D. Cotofana, M.J.M. Heijligers, J.T.J. Eijndhoven, Throughput Optimization via Cache Partitioning for Embedded Multiprocessors, Proceedings of the 6th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS, pp. 185-191, Samos, Greece, July 2006

- M.J.M. Heijligers, XeTaL-II: a low-power multi-processing SIMD architecture, MEDEA+ Design Automation Conference, Yachthotel Chiemsee, Germany, May 30 – June 01, 2006

- A. Molnos, S. D. Cotofana, M.J.M. Heijligers, J.T.J. Eijndhoven, Static Cache Partitioning Robustness Analysis for Embedded On Chip Multi Processors, Proceedings of the 2006 ACM International Conference on Computing Frontiers (CF’06), pp. 353 - 359, Ischia, Italy, May 2006

- A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J.T.J. Eijndhoven, Compositional, efficient caches for a chip multi-processor, Proceedings of Design, Automation and Test in Europe 2006 (DATE 06), pp. 345-351, Munich, Germany, March 2006

- B. Arts, L. Benini, N. van der Eng, M. Heijligers, A. Kenter, E. Macii, H. Munk, F. Theeuwen, Enhancing Behavioral-Level Design Flows with Statistical Power Estimation Capabilities, IEE Proc. Computers & Digital Techniques, 2005

- M.J.M. Heijligers, The role of re-configurable computing in platforms, MEDEA+ Design Automation Conference, Château des Mesnuls, France, May 24 – 26, 2005.

- A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J.T.J. Eijndhoven, Compositional memory systems for multimedia communicating tasks, Proceedings of 2005 Design, Automation and Test in Europe (DATE 2005), pp. 932-937, Munich, Germany, March 2005

- A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J.T.J. Eijndhoven, Inter-task sharing data and instructions in cache with enabling compositionality in parallel embedded systems, Proceedings of the 16th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2005, pp. 404-409, January 2005

- A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J.T.J. Eijndhoven, Cache Partitioning Options for Compositional Multimedia Applications, Proceedings of the 15th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC), pp. 86-90, Veldhoven, The Netherlands, November 2004

- A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J. T. J. van Eijndhoven, Compositional Memory Systems for Data Intensive Applications, Proceedings of Design, Automation and Test in Europe 2004 (DATE'04), pp. 728-729, Paris, France, February 2004

- M. Cocco, J. Dielissen, A. Hekstra, J. Huisken, M. Heijligers, A Scalable Architecture for LDPC decoding, Proceedings of Design, Automation and Test in Europe 2004 (DATE'04), pp. 728-729, Paris, France, February 2004

- A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J. T. J. van Eijndhoven, B. Mesman, Data Cache Optimization in Multimedia Applications, Proceedings of the 14th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2003, pp. 529-532, Veldhoven, The Netherlands, November 2003

- B. Arts, A. Bellu, L. Benini, N. Van der Eng, M. Heijligers, E. Macii, R. Maro, A. Milia, H. Munk, F. Theeuwen, Statistical Power Estimation for Behavioral Descriptions, PATMOS-03: 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 197-207, Torino, Italy, September 2003

- M.J.M. Heijligers, A. Hogenhuis, Analyzing architectural AspeCts of behavioral descriptions, Conference on Embedded System Design, pp. 239-250, Munich, 2000

- Luiz C. V. dos Santos , M. J. M. Heijligers, C. A. J. van Eijk ,J. Van Eijndhoven and J. A. G. Jess, A code-motion pruning technique for global scheduling, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 5, no. 1, pp. 1-38, 2000

- Sabih H. Gerez, Sonia M. Heemstra de Groot, Erwin R. Bonsma, Marc J.M. Heijligers, Overlapped Scheduling Techniques For High-Level Synthesis And Multiprocessor Realizations Of DSP Algorithms, In: J.C. Lopez, R. Hermida and W. Geisselhardt (Eds.), Advanced Techniques for Embedded System Design and Test, Kluwer Academic Publishers, pp 125-150, (1998).

- Wim Verhaegh, Gertjan Arnoldussen, Kees Goossens, and Marc Heijligers, " Phideo: architectural synthesis for high-throughput digital signal processing", in Philips Research Bulletin on IC Design, No. 31, pp. 9-11, 1997.

- L.V.J. Santos, M.J.M. Heijligers, C.A.J. van Eijk, J.T.J. van Eijndhoven and J.A.G. Jess, A constructive Method for Exploiting Code Motions, International Symposium on System Synthesis, 1996.

- M.J.M. Heijligers, The Application of Genetic Algorithms to High-Level Synthesis, Ph.D. thesis, Eindhoven University of Technology, 1991.

- M.J.M. Heijligers and J.A.G. Jess, High-Level Synthesis Scheduling and Allocation using Genetic Algorithms based on Constructive Topological Scheduling Techniques, Proceedings of the International Conference on Evolutionary Computation, pp. 56-61, 1995.

- M.J.M. Heijligers, L.J.M. Cluitmans and J.A.G. Jess, High-Level Synthesis Scheduling and Allocation using Genetic Algorithms, Proceedings of the Asia and South Pacific Design Automation Conference, pp. 61-66, 1995.

- M.J.M. Heijligers, H.A. Hilderink, A.H. Timmer and J.A.G. Jess, NEAT: an Object Oriented High-Level Synthesis Interface, Proceedings of the IEEE International Symposium on Circuits and Systems, pp 1.233-1.236, 1994.

- M.J.M. Heijligers, H.M.A.M. Arts, J.T.J. van Eijndhoven, H.A. Hilderink, J.A.G. Jess, W.J.M. Philipsen and A.H. Timmer, The New Eindhoven Architectural synthesis Toolbox, Proceedings of the Workshop on Circuits, Systems and Signal Processing, pp. 71-75, Houthalen, Belgium, 1993

- A.H. Timmer, M.J.M. Heijligers, L. Stok and J.A.G. Jess, Module Selection and Scheduling using Unrestricted Libraries, Proceedings of the EDAC/EuroASIC Conference, pp. 547-551, 1993.

- A.H. Timmer, M.J.M. Heijligers and J.A.G. Jess, Fast System-Level Area-Dela Curve Prediction, Proceedings of the APCHDLSA, pp. 198-207, 1993.

- M.J.M. Heijligers, H.M.A.M. Arts, J.T.J. van Eijndhoven, H.A. Hilderink, J.A.G. Jess, W.J.M. Philipsen and A.H. Timmer, Architectural Synthesis with NEAT++, FOM Workshop, Veldhoven, November 1992


Other Publications

WARNING: This section contains links to document files that may be covered by copyright. You may browse them at your convenience (in the same spirit as you may read a journal or a proceeding article in a public library). Retrieving, copying, or distributing these files, however, may violate the copyright protection law. We recommend that the user abides international law in accessing this directory.

- Marc Heijligers, Wat is het beste audio formaat?, iPodFan, voorjaar 2006.

- Marc Heijligers, Inside the iPod, Bright, Februari/Maart 2005.

- Marc Heijligers, De perceptie van high end, Audio & Techniek, pp. 11-15, no. 60, November 1997

- Marc Heijligers, A kind of sound, Jazz Magazine, 1999

- Marc Heijligers, Sala de audicion. Kind of Blue, in: Cuadernos de Jazz, #44, 1998