Polymer semiconducting devices are not new, and the subject has been a hot topic for the past 15 years or so. It is by now known how to create an organic light emitting diode, photovoltaic cell, or field-effect transistor (FET) but the open questions, and there are many, concern how to fabricate the materials more cheaply, and how to optimise their properties such that the morphology is optimal for their use. Here, we consider an FET.
Above: Diagram showing current flow in an organic FET. Most of the current flows in the organic semiconductor layer (in this case polyfluorene, or PFO) close to the border with the insulating polyimide layer.
In an unbiased FET a current cannot flow from the source to the drain because there are no charge carriers to do so. However, by applying an appropriate voltage to the gate (forward bias), this can be changed, and a current will flow. The current in a typical polymer FET will flow in the few nm at the interface between the semiconducting polymer and the dielectric material, which is often a polyimide (following the arrows in the diagram). However, this current flow is less efficient if the semiconducting polymers are not aligned (it does not matter too much how they are aligned, just that they are). Such polymers, such as polyfluorene (PFO) usually align, because they can form crystalline phases.
A rough interface may be enough to disrupt the alignment, and so to investigate this interface, we performed neutron reflectometry measurements on the interface between polyfluorene and poly(methyl methacrylate) (PMMA) [1].
PMMA is an amorphous model polymer that can be used as a model dielectric material, even if its low dielectric constant precludes its use in real devices.
The NR experiments revealed that the interface width when the bilayer was heated at temperature corresponding to the nematic phase (no positional order, but the molecules "point" in a certain direction) of the PFO (2 nm) is somewhat broader than when the PFO is crystalline (1 nm). The breadth of the interface is in a range that corresponds to the the size of the carrier transport layer.
Experiments are now being performed to compare the interfacial widths with transistor performance using novel FET structures [2].
References
[1] A. M. Higgins, P. C. Jukes, S. J. Martin, M. Geoghegan, R. A. L. Jones, and R. Cubitt Appl. Phys. Lett. 81 4949-51 (2002).
[2] J. C. Pinto, G. L. Whiting, S. Khodabakhsh, L. Torre, A. B. Rodríguez, R. M. Dalgliesh, A. M. Higgins, J. W. Andreasen, M. M. Nielsen, M. Geoghegan, W. T. S. Huck, and H. Sirringhaus Adv. Funct. Mater. accepted.